? integrated circuits group lh 28 f 008 sc t -l 12 fla sh me mor y 8 m ( 1 m 8 ) (model no.: lh f 08 ch 3 ) spec no.: el 10 4 1 64 b issue date: may 7 , 19 99 p roduc t s pecific a tions
sharp lhf08ch3 l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics *instrumentation and measuring equipment *machine tools @audiovisual equipment *home appliance *communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands hiqh reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. &ontrol and safety devices for airplanes, trains, automobiles, and other transportation equipment l mainframe computers l traffic control systems *gas leak detectors and automatic cutoff devices *rescue and security equipment mother safety devices and safety equipment,etc. (3) do not use the products covered herein for the following equipment which demands extremelv hiqh performance in terms of functionality, reliability, or accuracy. l aerospace equipment *communications equipment for trunk lines *control equipment for the nuclear power industry @medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. paw i 1
shari= lhf08ch3 1 contents page page 1.0 introduction ................................................... 3 1.1 new features.. .................................................... 3 1.2 product overview ................................................ 3 2.0 principles of operation.. ........................... 7 2.1 data protection ................................................... 7 3.0 bus operation ................................................. a 3.1 read ................................................................... a 3.2 output disable .................................................... 6 3.3 standby ............................................................... a 3.4 deep power-down .............................................. 8 3.5 read identifier codes operation.. ....................... 9 3.6 write .................................................................... 9 5.0 design considerations ............................. .23 5.1 three-line output control ................................ .23 5.2 ry/by# and block erase, byte write and lock-bit configuration polling.. ......................................... 23 5.3 power supply decoupling.. ................................ 23 5.4 v,, trace on printed circuit boards.. ............... .23 5.5 v,,, v,,, rp# transitions.. .............................. .24 5.6 power-up/down protection.. ............................. .24 5.7 power dissipation .............................................. 24 4.0 command definitions .................................... 9 4.1 read array command.. ..................................... 12 4.2 read identifier codes command ...................... 12 4.3 read status register command.. ..................... 12 4.4 clear status register command.. ..................... 12 4.5 block erase command.. .................................... 12 4.6 byte write command ........................................ 13 4.7 block erase suspend command.. ..................... 13 4.6 byte write suspend command.. ....................... 14 4.9 set block and master lock-bit commands.. ..... 14 4.10 clear block lock-bits command.. ................... 15 6.0 electrical specifications.. ..................... .25 6.1 absolute maximum ratings ............................... 25 6.2 operating conditions ......................................... 25 6.2.1 capacitance ................................................. 25 6.2.2 ac input/output test conditions.. ............... .26 6.2.3 dc characteristics ........................................ 27 6.2.4 ac characteristics - read-only operations .29 6.2.5 ac characteristics - write operations.. ....... .32 6.2.6 alternative ce#-controlled writes.. ............. .35 6.2.7 reset operations ......................................... 36 6.2.6 block erase, byte write and lock-bit configuration performance ........................... 39 7.0 additional information ............................ .40 7.1 ordering information ......................................... .40 8.0 package and packing specifications ..4 1 rev. 1.0
shai?p lhf08ch3 2 lh28foossct-l12 8m-bit (1 mb x 8) smartvoltage flash memory n smartvoltage technology - 2.7v(read-only), 3.3v or 5v vcc - 3.3v, 5v or 12v vpp n high-performance read access time - 120ns(5v*0.5v), 150ns(3.3v*o.3v), 170ns(2.7v-3.6v) n operating temperature - 0c to +7o?c i high-density symmetrically-blocked architecture - sixteen 64k-byte erasable blocks i low power management - deep power-down mode - automatic power savings mode decreases ice in static mode i enhanced data protection features - absolute protection with vpp=gnd - flexible block locking - block erase/byte write lockout during power transitions n automated byte write and block erase - command user interface - status register n enhanced automated suspend options - byte write suspend to read - block erase suspend to byte write - block erase suspend to read n extended cycling capability - 100,000 block erase cycles - 1.6 million block erase cycles/chip n sram-compatible write interface n industry-standard packaging - 40-lead tsop n etoxtm* nonvolatile flash techno wy w cmos process (p-type silicon substrate) n not designed or rated as radiation hardened sharp?s LH28F008SCT-L12 flash memory with smartvoltage technology is a high-density, low-cost, nonvolatile, ?ead/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F008SCT-L12 offers three levels of protection: absolute protection with v,, at znd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the LH28F008SCT-L12 is manufactured on sharp?s 0.38um etoxtm process technology. it come in ndustry-standard package: the 40-lead tsop, ideal for board constrained applications. based on the 28f008sa architecture, the LH28F008SCT-L12 enables quick and easy upgrades for designs demanding the state-of-the-art. ?etox is a trademark of intel corporation. rev. 1.3
lhf08ch3 3 1 introduction this datasheet contains LH28F008SCT-L12 specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. LH28F008SCT-L12 flash memory documentation also includes application notes and design tools which are referenced in section 7. 1.1 new features the LH28F008SCT-L12 smartvoltage flash memory maintains backwards-compatibility with sharp?s 28f008sa. key enhancements over the 28f008sa include: *smartvoltage technology *enhanced suspend capabilities &r-system block locking both devices share a compatible pinout, status register, and software command set. these similarities enable a clean upgrade from the 28f008sa to LH28F008SCT-L12. when upgrading, it is important to note the following differences: *because of new feature support, the two devices have different device codes. this allows for software optimization. l vpplk has been lowered from 6.5v to l.5v to support 3.3v and 5v block erase, byte write, and lock-bit configuration operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smartvoltage technology, allow v,, connection to 3.3v or 5v. 1.2 product overview the LH28F008SCT-L12 is a high-performance 8m-bit smartvoltage flash memory organized as 1 m-byte of 3 bits. the im-byte of data is arranged in sixteen sk-byte blocks which are individually erasable, ockable, and unlockable in-system. the memory nap is shown in figure 3. smartvoltage technology provides a choice of voc and v,, combinations, as shown in table 1, to mee system performance and power expectations. 2.7\ v,, consumes approximately one-fifth the power o 5v vo,. but, 5v vco provides the highest reac performance. v,, at 3.3v and 5v eliminates the neec for a separate 12v converter, while v,,=12\ maximizes block erase and byte write performance in addition to flexible erase and program voltages the dedicated v,, pin gives complete data protectior when v,+v,,,,. table 1. vc, and v,, voltage combinations offered by smartvoltage technology vr.r: voltage vpp voltage 2.7v(?) - -.. 3.3v 3.3v, 54, l2v 5v 5v. 12v i note: 1. block erase, byte write and lock-bit configuratior operations with v,o<3.ov are not supported. internal vcc and vp, detection circuitb automatically configures the device for optimizec read and write operations. a command user interface (cui) serves as the interface between the system processor and interna operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. a block erase operation erases one of the device?s 64k-byte blocks typically within 0.3s (5v v,,, 12v vp,) independent of other blocks. each block can be independently erased 100,000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in byte increments typically within 6u.s (5v vcc, 12v vpp). byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.3
lhf08ch3 4 individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit jates block lock-bit modification. lock-bit zonfiguration operations (set block lock-bit, set master lock-bit, and clear block lock-bits zommands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, byte write, or lock-bit configuration operation is iinished. the ry/by# output gives an additional indicator of jvsm activity by providing both a hardware signal of status (versus software polling) and status masking iinterrupt masking for background block erase, for mample). status polling using ry/by# minimizes 30th cpu overhead and system power consumption. jvhen low, ry/by# indicates that the wsm is 3erforming a block erase, byte write, or lock-bit zonfiguration. ry/by#-high indicates that the wsm is ,eady for a new command, block erase is suspended :and byte write is inactive), byte write is suspended, 3r the device is in deep power-down mode. the access time is 120 ns (tavav) over the commercial temperature range (0% to +70?(z) ant vc, supply voltage range of 4.5v-5.5v. at lower vcc voltages, the access times are 150 ns (3.ov-3.6v: and 170 ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i,,, current is 1 ma at 5v v,,. when ce# and rp# pins are at v,,, the i,, cmos standby mode is enabled. when the rp# pin is a gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs arc valid. likewise, the device has a wake time (t,,,,: from rp#-high until writes to the cui are recognized with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 40-lead tsop (thin smal outline package, 1.2 mm thick). pinout is shown ir figure 2. rev.1.0
sharp lhf08ch3 5 figure 1. block diagram 49 ale a17 a16 ais a14 an a12 ce# vcc vpp rp# 41 alo as 43 a7 a6 a5 a4 40-lead tsop standard pinout 1 omm x 20mm top view nc nc we# oe# ry/by# dq7 dq6 dq5 dq4 vcc gnd gnd dq3 dq2 dqi dqo z a2 a3 figure 2. tsop 40-lead pinout rev. 1.0
sharp r r lhf08ch3 6 i symbol a,-al 9 dqo-dq7 ce# rp# oe# we# ry/by# output vcc gnd nc type input t input/ output input input input input supply supply supply name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. rp# at v,, enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp#=v,, overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with vihcrp# sharp lhf08ch3 7 2 principles of operation the LH28F008SCT-L12 smartvoltage flash memory includes an on-chip wsm to manage block erase, byte write, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register and identifier codes can be accessed through the cui independent of the v,, voltage. high voltage on v,, enables successful block erasure, byte writing, and lock-bit configuration. all functions associated with altering memory contents-block erase, byte write, lock-bit configuration, status, and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, byte write, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or write data from any other block. byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. 2: 1 data protection fffff foooo effff eoow dffff do000 cffff coooo bffff boo00 affff aoow sffff 90000 8ffff 80000 7ffff 70000 6ffff 60000 sffff 50000 4ffff 40000 jffff 30000 pffff 20000 1 ffff 10000 offff figure 3. memory map depending on the application, the system designer may choose to make the v,, power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to v,,,,,z13. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vpp~vpplk, memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v,,. all write functions are disabled when vcc is below the write lockout voltage vlko or when rp# is at v,,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. rev.1.3
sharp lhf08ch3 8 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, or status register independent of the v,, voltage. rp# can be at either v,, or v,,. the first task is to write the appropriate read mode command (read array, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. four control pins dictate the data flow in and out of the component: ce#, oe#, we#, and rp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq,-dq,) control and when active drives the selected memory data onto the i/o bus. we# must be at v,, and rp# must be at v,, or v,,. figure 15 illustrates a read cycle. 3.2 output disable jvith oe# at a logic-high level (v,,), the device outputs are disabled. output pins dc+,-dq, are olaced in a high-impedance state. 3.3 standby ze# at a logic-high level (vi,) places the device in standby mode #which substantially reduces device lower consumption. dqc-dq, outputs are placed in i high-impedance state independent of oe#. if deselected during block erase, byte write, or lock-bit :onfiguration, the device continues functioning, and consuming active power until the operatior completes. 3.4 deep power-down rp# at v,, initiates the deep power-down mode. in read modes, rp#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. rp# must be held low fo a minimum of 100 ns. time tphqv is required afte return from power-down until initial memory acces: outputs are valid. after this wake-up interval, norma operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, configuration modes, ,?;~low~ritell o;bo~ck;+; operation. ry/by# remains low until the rese operation is complete. memory contents beins altered are no longer valid; the data may be partially erased or written. time tphwl is requirod after rpb goes to logic-high (v,,) before another command car be written. as with any automated device, it is important tc assert rp# during system reset. when the systen- comes out of reset, it expects to read from the flask memory. automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. if a cpu resei occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1.0
lhf08ch3 9 3.5 read identifier codes operation 3.6 write the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. writing commands to the cui enable reading 01 device data and identifier codes. they also control inspection and clearing of the status register. when vpp=vpphli2/3~ the cui additionally controls block erasure, byte write, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to 5s erased. the byte write command requires the command and address of the location to be written. set master and block lock-bit commands require ths command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. fffff foo04 foo03 foo02 reserved for future implementation block 15 lock configuration code 100021 10001 10000 offff block 1 lock configuration code master lock configuration code 00002 t ----------------- block 0 lock configuration code l------------------------------------ 00001~ device code manufacturer code block (i figure 4. device identifier code memory map the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a commanc are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 16 and 17 illustrate we# and ce#-controlled write operations. 4 command definitions when the v,, voltage 5 v,,,,, read operations from the status register, identifier codes, or blocks are enabled. placing v,,,,,,, on v,, enables successful block erase, byte write and lock-bii configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. l rpv i n
shari= lhf08ch3 10 mode read output disable table 3. bus operations notes rp# ce# oe# we# address vpp d&.-r ry/by# 1,2,3,8 vt or ?il ?il ?i, x x hh dout x 3 ?i, or vr# ?il ?i, ?1, x x high z x standby 3 ?i, or vhh ?i, x x x x high z x deep power-down 4 v,, x x x x x high z vn,, read identifier codes 8 ?i, or vhh ?il ?il vlh see figure 4 ? note 5 ?oh write 3,6,7,8 ?. or hh ?il ?i, ?il x x dln x ?4otes: i. refer to dc characteristics. when vpp lhf08ch3 us cycle second bus cycle , jdr(2) 1 data(?) oper(?) 1 addr12) 1 datat3) read array/reset 1 1 write 1 x 1 ffh command table 4. command definit bus cycles first b rea?d. notes ooer(l) 1 ad ions(g) 11 read identifier codes 1 22 i 4 i write i x i 90h i read i ia i id /i read status register clear status register block erase 2 1 2 write x 70h read x srd write x 50h 5 write ba 20h write ba doh 40h ii byte write 2 5,6 write wa l& write wa wd id byte write 1 5 write x boh i id byte write 1 5 write x doh resume set block lock-bit set master lock-bit clear block lock-bits notes: 1. bus operations are defined in table 3. 2. x=any valid address within the device. ia=ldentifier code address: see figure 4. 1 2 7 write ba 60h write ba olh 2 7 write x 60h write x flh 2 8 write x 60h write x doh ba=address within the block being erased or locked. wa=address of memory location to be written. 3. srd=data read from status register. see table 7 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see section 4.2 for read identifier code data. 5. if the block is locked, rp# must be at v,, to enable block erase or byte write operations. attempts to issue a block erase or byte write to a locked block while rp# is v,,. 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. if the master lock-bit is set, rp# must be at v,, to set a block lock-bit. rp# must be at v,, to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is v,,. 8. if the master lock-bit is set, rp# must be at v,, to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is vi,. 9. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1.0
lhfosch3 12 4.1 read array command 4.3 read status register command upon initial device power-up and after exit from deep dower-down mode, the device defaults to read array node. this operation is also initiated by writing the read array command. the device remains enabled ?or reads until another command is written. once the nternal wsm has started a block erase, byte write or ock-bit configuration, the device will not recognize :he read array command until the wsm completes ts operation unless the wsm is suspended via an erase suspend or byte write suspend command. the read array command functions independently of :he v,, voltage and rp# can be vi, or v,,. 4.2 read identifier codes command the identifier code operation is initiated by writing the qead identifier codes command. following the :ommand write, read cycles from addresses shown in =igure 4 retrieve the manufacturer, device, block lock :onfiguration and master lock configuration codes see table 5 for identifier code values). to terminate :he operation, write another valid command. like the ?ead array command, the read identifier codes :ommand functions independently of the v,, voltage lnd rp# can be v,, or v,,. following the read dentifier codes command, the following information :an be read: table 5. identifier codes *block is unlocked @block is locked *reserved for future use master lock configuration *device is unlocked odevice is locked *reserved for future use 4ote: . x selects the specific block lock configuration code to be read. see figure 4 for the device identifier code memory map. the status register may be read to determine when e block erase, byte write, or lock-bit configuration i: complete and whether the operation completec successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations outpu data from the status register until another valic command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to vi, before further reads to update the status register latch. the reac status register command functions independently o? the v,, voltage. rp# can be v,, or v,,. 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.l are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 7). by allowing system software to reset these bits, severa operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence: may be performed. the status register may be pollee to determine if an error occurre during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v,, voltage. rp# can be vi, or v,,. this command is not functional during block erase or byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. rev. 1.0
lhf08ch3 13 when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1 ?i. also, reliable block erasure can only occur when vcc=vcc2,s and vpp=vpph1,2,3. in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v,,iv,,,k, sr.3 and sr.5 will be set to ?1 ?i. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp#=v,,. if block erase is attempted when the corresponding block lock-bit is set and rp#=v,,, sr.l and sr.5 will be set to ?1?. block erase operations with v,, |